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DTSTART:19700308T020000
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DTSTAMP:20181221T160725Z
LOCATION:D170
DTSTART;TZID=America/Chicago:20181111T103000
DTEND;TZID=America/Chicago:20181111T105200
UID:submissions.supercomputing.org_SC18_sess149_ws_mchpc105@linklings.com
SUMMARY:Challenges of High-Capacity DRAM Stacks and Potential Directions
DESCRIPTION:Workshop\nMemory, NVRAM, Parallel Programming Languages, Libra
 ries, and Models, Workshop Reg Pass\n\nChallenges of High-Capacity DRAM St
 acks and Potential Directions\n\nFarmahini-Farahani, Gurumurthi, Loh, Igna
 towski\n\nWith rapid growth in data volumes and an increase in number of C
 PU/GPU cores per chip, the capacity and bandwidth of main memory can be sc
 aled up to accommodate performance requirements of data-intensive applicat
 ions. Recent 3D-stacked in-package memory devices such as high-bandwidth m
 emory (HBM) and similar technologies can provide high amounts of memory ba
 ndwidth at low access energy. However, 3D-stacked in-package memory have l
 imited memory capacity. In this paper, we study and present challenges of 
 scaling the capacity of 3D-stacked memory devices by stacking more DRAM di
 es within a device and building taller memory stacks. We also present pote
 ntial directions and mitigations to building tall HBM stacks of DRAM dies.
  Although taller stacks are a potentially interesting approach to increase
  HBM capacity, we show that more research is needed to enable high-capacit
 y memory stacks while simultaneously scaling up their memory bandwidth. Sp
 ecifically, alternative bonding and stacking technologies can be investiga
 ted as a potentially major enabler of tall HBM stacks.
URL:https://sc18.supercomputing.org/presentation/?id=ws_mchpc105&sess=sess
 149
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