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UID:submissions.supercomputing.org_SC18_sess149@linklings.com
SUMMARY:MCHPC’18: Workshop on Memory Centric High Performance Computing
DESCRIPTION:Workshop\nMemory, NVRAM, Parallel Programming Languages, Libra
 ries, and Models, Workshop Reg Pass\n\nOn the Applicability of PEBS-Based 
 Online Memory Access Tracking for Heterogeneous Memory Management at Scale
 \n\nRoca Nonell, Gerofi, Bautista-Gomez, Martinet, Beltran Querol...\n\nOp
 erating systems have historically had to manage only a single type of memo
 ry device. The imminent availability of heterogeneous memory devices based
  on emerging memory technologies confronts the classic single memory model
  and opens a new spectrum of possibilities for memory management. Transpar
 en...\n\n---------------------\nChallenges of High-Capacity DRAM Stacks an
 d Potential Directions\n\nFarmahini-Farahani, Gurumurthi, Loh, Ignatowski\
 n\nWith rapid growth in data volumes and an increase in number of CPU/GPU 
 cores per chip, the capacity and bandwidth of main memory can be scaled up
  to accommodate performance requirements of data-intensive applications. R
 ecent 3D-stacked in-package memory devices such as high-bandwidth memory (
 HBM) an...\n\n---------------------\nIntroduction - MCHPC’18: Workshop on 
 Memory Centric High Performance Computing\n\nYan, Brightwell, Sun, Gokhale
 \n\nThe growing disparity between CPU speed and memory speed, known as the
  memory wall problem, has been one of the most critical and long-standing 
 challenges in the computing industry. The situation is further complicated
  by the recent expansion of the memory hierarchy, which is becoming deeper
  and mor...\n\n---------------------\nEvaluation of Intel Memory Drive Tec
 hnology Performance for Scientific Applications\n\nMironov, Kudryavtsev, A
 lexeev, Moskovsky, Kulikov...\n\nIn this paper, we present benchmark data 
 for Intel Memory Drive Technology (IMDT), which is a new generation of Sof
 tware-defined Memory (SDM) based on Intel ScaleMP collaboration and using 
 3D XPoint TM based Intel Solid-State Drives (SSDs) called Optane. We studi
 ed IMDT performance for synthetic ben...\n\n---------------------\nA Preli
 minary Study of Compiler Transformations for Graph Applications on the Emu
  System\n\nChatarasi, Sarkar\n\nUnlike dense linear algebra applications, 
 graph applications typically suffer from poor performance because of 1) in
 efficient utilization of memory systems through random memory accesses to 
 graph data, and 2) overhead of executing atomic operations. Hence, there i
 s a rapid growth in improving both s...\n\n---------------------\nMCHPC'18
  Panel:  Research Challenges in Memory-Centric Computing\n\nGokhale\n\n---
 ------------------\nHeterogeneous Memory and Arena-Based Heap Allocation\n
 \nWilliams, Ionkov, Lang, Lee\n\nNonuniform Memory Access (NUMA) will like
 ly continue to be the chief abstraction used to expose heterogeneous memor
 y. One major problem with using NUMA in this way is, the assignment of mem
 ory to devices, mediated by the hardware and Linux OS, is only resolved to
  page granularity. That is, pages, no...\n\n---------------------\nMCHPC'1
 8 Afternoon Keynote: All Tomorrow’s Memory Systems\n\nJacob\n\nMemory and 
 communication are the primary reasons that our time-to-solution is no bett
 er than it currently is … the memory system is slow; the communication ove
 rhead is high; and yet a significant amount of research is still focused o
 n increasing processor performance, rather than decreasing (the cos...\n\n
 ---------------------\nData Placement Optimization in GPU Memory Hierarchy
  Using Predictive Modeling\n\nStoltzfus, Emani, Lin, Liao\n\nModern superc
 omputers often use Graphic Processing Units (or GPUs) to meet the ever-gro
 wing demands for high performance computing. GPUs typically have a complex
  memory architecture with various types of memories and caches, such as gl
 obal memory, shared memory, constant memory, and texture memory.T...\n\n--
 -------------------\nUnderstanding Application Recomputability without Cra
 sh Consistency in Non-Volatile Memory\n\nRen, Wu, Li\n\nEmerging non-volat
 ile memory (NVM) is promising to be used as main memory, because of its go
 od performance, density, and energy efficiency.  Leveraging the non-volati
 lity of NVM as main memory, we can recover data objects and resume applica
 tion computation (recomputation) after application crashes. ...\n\n-------
 --------------\nWorkshop Lunch (on your own)\n\n\n\n---------------------\
 nExploring Allocation Policies in Disaggregated Non-Volatile Memories\n\nK
 ommareddy, Hughes, Hammond, Awad\n\nMany modern applications have memory f
 ootprints that are increasingly large, driving system memory capacities hi
 gher and higher. However, due to the diversity of applications that run on
  High-Performance Computing (HPC) systems, the memory utilization can fluc
 tuate widely from one application to ano...\n\n---------------------\nxBGA
 S: Toward a RISC-V ISA Extension for Global, Scalable, Shared Memory\n\nLe
 idel, Wang, Chen, Donofrio, Fatollahi-Fard...\n\nGiven the switch from mon
 olithic architectures to integrated systems of commodity components, scala
 ble high performance computing architectures often suffer from unwanted la
 tencies when operations depart an individual device domain.  Transferring 
 control and/or data across loosely coupled commodity ...\n\n--------------
 -------\nWorkshop Afternoon Break\n\n\n\n---------------------\nWorkshop M
 orning Break\n\n\n\n---------------------\nMCHPC'18 Morning Keynote: Conve
 rging Storage and Memory\n\nHady\n\nOrder of magnitude advances in non-vol
 atile memory density and performance are upon us bringing significant syst
 ems level architecture opportunities. The NAND Memory transition to 3D and
  the introduction of QLC have recently increased NAND SSD storage density 
 at a very rapid pace. Products featuring...\n
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