BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20181221T160729Z
LOCATION:C140/142
DTSTART;TZID=America/Chicago:20181113T103000
DTEND;TZID=America/Chicago:20181113T110000
UID:submissions.supercomputing.org_SC18_sess194_pap147@linklings.com
SUMMARY:Exploiting Idle Resources in a High-Radix Switch for Supplemental 
 Storage
DESCRIPTION:Paper\nArchitectures, Data Analytics, Networks, Tech Program R
 eg Pass, BP Finalist\n\nExploiting Idle Resources in a High-Radix Switch f
 or Supplemental Storage\n\nBlumrich, Jiang, Dennison\n\nA general-purpose 
 switch for a high-performance network is usually designed with symmetric p
 orts providing credit-based flow control and error recovery via link-level
  retransmission. Because port buffers must be sized for the longest links 
 and modern asymmetric network topologies have a wide range of link lengths
 , we observe that there can be a significant amount of unused buffer memor
 y, particularly in edge switches. We also observe that the tiled architect
 ure used in many high-radix switches contains an abundance of internal ban
 dwidth. We combine these observations to create a new switch architecture 
 that allows ports to stash packets in unused buffers on other ports, acces
 sible via excess internal bandwidth in the tiled switch. We explore this a
 rchitecture through two use cases: end-to-end resilience and congestion mi
 tigation. We find that stashing is highly effective and does not negativel
 y impact network performance.
URL:https://sc18.supercomputing.org/presentation/?id=pap147&sess=sess194
END:VEVENT
END:VCALENDAR

