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DTSTAMP:20181221T160910Z
LOCATION:C146
DTSTART;TZID=America/Chicago:20181114T133000
DTEND;TZID=America/Chicago:20181114T150000
UID:submissions.supercomputing.org_SC18_sess216@linklings.com
SUMMARY:Resilience 2
DESCRIPTION:Paper\nPerformance, Resiliency, Tools, Tech Program Reg Pass\n
 \nLessons Learned from Memory Errors Observed Over the Lifetime of Cielo\n
 \nLevy, Ferreira, DeBardeleben, Siddiqua, Sridharan...\n\nMaintaining the 
 performance of high-performance computing (HPC) applications as failures i
 ncrease is a major challenge for next-generation extreme-scale systems. Re
 cent research demonstrates that hardware failures are expected to become m
 ore common due to increased component counts, reduced device-f...\n\n-----
 ----------------\nEvaluating and Accelerating High-Fidelity Error Injectio
 n for HPC\n\nChang, Lym, Kelly, Sullivan, Erez\n\nWe address two important
  concerns in the analysis of the behavior of applications in the presence 
 of hardware errors: (1) when is it important to model how hardware faults 
 lead to erroneous values (instruction-level errors) with high fidelity, as
  opposed to using simple bit-flipping models, and (2) ...\n\n-------------
 --------\nPartial Redundancy in HPC Systems with Non-Uniform Node Reliabil
 ities\n\nHussain, Znati, Melhem\n\nWe study the usefulness of partial redu
 ndancy in HPC message passing systems where individual node failure distri
 butions are not identical. Prior research works on fault tolerance have ge
 nerally assumed identical failure distributions for the nodes of the syste
 m. In such settings, partial replicatio...\n
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