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DTSTAMP:20181221T160906Z
LOCATION:C144
DTSTART;TZID=America/Chicago:20181111T133000
DTEND;TZID=America/Chicago:20181111T170000
UID:submissions.supercomputing.org_SC18_sess250_tut147@linklings.com
SUMMARY:Productive Parallel Programming for FPGA with High-Level Synthesis
DESCRIPTION:Tutorial\nHeterogeneous Systems, Parallel Programming Language
 s, Libraries, and Models, Tutorial Reg Pass\n\nProductive Parallel Program
 ming for FPGA with High-Level Synthesis\n\nde Fine Licht, Hoefler\n\nAs th
 e scale of large high performance computing systems increases, so does the
 ir power consumption, making energy efficiency a first class citizen in th
 eir design. While GPUs and custom processors have improved this situation 
 significantly, reconfigurable architectures, such as FPGAs, promise anothe
 r major step in energy efficiency, constituting a middle ground between fi
 xed hardware architectures and custom-built ASICs. \n\nProgramming FPGAs h
 as traditionally been done in hardware description languages, requiring ex
 tensive hardware knowledge and significant engineering effort.  This tutor
 ial shows how high-level synthesis (HLS) can be harnessed to productively 
 achieve scalable pipeline parallelism on FPGAs. Attendees will learn how t
 o target FPGA resources from high-level C++ or OpenCL code, guiding the ma
 pping from imperative code to hardware, enabling them to develop massively
  parallel designs with real performance benefits. \nWe treat concrete exam
 ples well known from the software world, relating traditional code optimiz
 ations to both corresponding and new transformations for hardware, buildin
 g on existing knowledge when introducing new topics. By bridging the gap b
 etween software and hardware optimization, our tutorial aims to enable dev
 elopers from a larger set of backgrounds to start tapping into the potenti
 al of FPGAs with real high performance codes.
URL:https://sc18.supercomputing.org/presentation/?id=tut147&sess=sess250
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