BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20181221T160904Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T083000
DTEND;TZID=America/Chicago:20181113T170000
UID:submissions.supercomputing.org_SC18_sess322_post113@linklings.com
SUMMARY:Hardware Acceleration of CNNs with Coherent FPGAs
DESCRIPTION:Poster\nTech Program Reg Pass, Exhibits Reg Pass\n\nHardware A
 cceleration of CNNs with Coherent FPGAs\n\nSefat, Aslan, Qasem\n\nThis pap
 er describes a new flexible approach to implementing energy-efficient CNNs
  on FPGAs. Our design leverages the Coherent Accelerator Processor Interfa
 ce (CAPI) which provides a cache-coherent view of system memory to attache
 d accelerators. Convolution layers are formulated as matrix multiplication
  kernels and then accelerated on CAPI-supported Kintex FPGA board. Our imp
 lementation bypasses the need for device driver code and significantly red
 uces the communication and I/O transfer overhead. To improve the performan
 ce of the entire application, not just the convolution layers, we propose 
 a collaborative model of execution in which the control of the data flow w
 ithin the accelerator is kept independent, freeing-up CPU cores to work on
  other parts of the application. For further performance enhancements, we 
 propose a technique to exploit data locality in the cache, situated in the
  CAPI Power Service Layer (PSL). Finally, we develop a resource-conscious 
 implementation for more efficient utilization of resources and improved sc
 alability.
URL:https://sc18.supercomputing.org/presentation/?id=post113&sess=sess322
END:VEVENT
END:VCALENDAR