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DTSTAMP:20181221T160904Z
LOCATION:C2/3/4 Ballroom
DTSTART;TZID=America/Chicago:20181113T083000
DTEND;TZID=America/Chicago:20181113T170000
UID:submissions.supercomputing.org_SC18_sess322_post160@linklings.com
SUMMARY:Energy Efficiency of Reconfigurable Caches on FPGAs
DESCRIPTION:Poster\nTech Program Reg Pass, Exhibits Reg Pass\n\nEnergy Eff
 iciency of Reconfigurable Caches on FPGAs\n\nWang, Li, Geng, Herbordt\n\nT
 he performance of a given cache architecture depends largely on the applic
 ations that run on it. Even though each application has its best-suited ca
 che configuration, vendors of fixed HPC systems must provide compromise de
 signs. Reconfigurable caches can adjust cache configuration dynamically to
  get best-suited cache parameters in runtime and notably reduce energy con
 sumption.  For example, when it is possible to deploy a low capacity low a
 ssociativity design without increasing the miss rate substantially. For mo
 dern multi-core processors, each core's memory access behavior can be infl
 uenced by other cores. So it is more complicated to design reconfigurable 
 caches for them. \n\nIn this paper, a design for a reconfigurable cache on
  FPGAs is presented that can run in modes with different capacities, assoc
 iativity. We demonstrate that better performance and energy efficiency can
  be achieved by tuning these cache parameters at runtime.
URL:https://sc18.supercomputing.org/presentation/?id=post160&sess=sess322
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